一种环形栅LDMOS器件的宏模型

提出了一种适用于环形栅LDMOS器件的子电路宏模型。基于对环形栅LDMOS器件结构的分析, 将环形栅LDMOS器件分为两个部分, 一个是中间的条形栅MOS部分, 使用常规的高压MOS模型; 另一个是端头部分, 为一个圆环形栅极MOS器件, 采用了一个单独的模型。基于40 V BCD工艺的N沟道LDMOS器件进行模型提取与验证。结果表明, 建立的宏模型具有较强的几何尺寸缩放功能, 对于不同尺寸的器件都具有较高的拟合精度, 并且模型能够兼容当前主要的商用电路仿真器Hspice和Spectre。

Abstract

A Spice sub-circuit macro model for annular gate LDMOS is presented. The macro model divided the annular gate LDMOS into two parts based on its structure. The middle part of annular gate LDMOS was a conventional LDMOS transistor whit rectangle gate. The terminal part was an annular gate LDMOS, and it was modeled individually. The macro model was verified by the N channel LDMOS in a 40 V BCD process. The results show that the macro model has good ability of geometry scaling and it can fit the characteristics curves of different size devices exactly. The macro model is compatible with commercial circuit simulator Hspice and Spectre.

参考文献

[1] 张波, 肖立伊, 付方发. 基于电场分布特性的环形栅器件SPICE模型研究［J］. 微电子学与计算机, 2012, 29(12)： 140-144.

[2] BEZHENOVA V, MICHALOWSKA-FORSYTH A. Modeling of annular gate MOS transistor ［C］ // 2018 18th European Conference on Radiation and its Effects on Components and Systems (RADECS). Goteborg, Sweden. 2018: 44-47.

[3] STROHBEHN K, MARTIN M N. SPICE macro models for annular MOSFETs ［C］ // 2004 IEEE Aerospace Conference Proceedings. Big Sky, MT, USA. 2004: 2370-2377.

[4] LOPEZ P, BLANCO-FILGUERIA B, HAUER J. Modeling and experimental results of short channel annular MOS transistors ［C］ // 2011 20th European Conference on Circuit Theory and Design (ECCTD). Linkping, Sweden. 2011: 685-688.

[5] XIA K, INDANA H, GOGINENI U. Compact modeling of LDMOS working in the third quadrant ［C］ // Proceedings of the IEEE 2014 Custom Integrated Circuits Conference. San Jose, CA, USA. 2014: 821-824.

[6] IIZUKA T, NAVARRO D, MIURA-MATTAUSCH M, et al. Predictive compact modeling of abnormal LDMOS characteristics due to overlap-length modification ［C］ // 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). Kobe, Japan. 2020: 157-160.

[7] 徐文杰, 孙玲玲, 刘军, 等. 一个连续且解析的SOI LDMOS表面势模型［J］. 半导体学报, 2007, 28(11)：1712-1716.

[8] 李海松, 孙伟锋, 易扬波, 等. PDP驱动芯片中高压LDMOS建模［J］. 半导体学报, 2008, 29(11)：2110-2114.

[9] DEY S, SONNET A, VARGHESE D, et al Generalized sub-circuit model to enable accurate CHC aging simulation and spatial defect profiling in LDMOS ［C］ // 2022 34th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD). Vancouver, BC, Canada. 2022: 241-244.

[10] SASSE G T, SUBRAMANIAN V, RADIC L. Aging models for n- and p-type LDMOS covering low medium and high VGS operation ［C］ // 2021 IEEE International Reliability Physics Symposium (IRPS). Monterey, CA, USA. 2021: 751-756.

[11] MAHAJAN B K, CHEN Y P, ALAM M A, et al. A critical examination of the TCAD modeling of hot carrier degradation for LDMOS transistors ［C］ // 2022 IEEE International Reliability Physics Symposium (IRPS). Dallas, TX, USA. 2022: 10A.2-1-10A.2-7.

[12] HASTINGS A. 模拟电路版图的艺术［M］. 第2版. 张为, 译. 北京：电子工业出版社, 2007： 397-398.

韩卫敏, 刘娇, 王磊, 洪敏, 朱坤峰, 张广胜. 一种环形栅LDMOS器件的宏模型[J]. 微电子学, 2023, 53(3): 500. HAN Weimin, LIU Jiao, WANG Lei, HONG Ming, ZHU Kunfeng, ZHANG Guangsheng. A Macro Model for LDMOS with Annular Gate[J]. Microelectronics, 2023, 53(3): 500.

一种环形栅LDMOS器件的宏模型

关于本站 Cookie 的使用提示

全站搜索

一种环形栅LDMOS器件的宏模型

相关论文

相关资讯

关于本站 Cookie 的使用提示

全站搜索