一种适用于100 Gbit/s以太网PCS的高速异步FIFO

采用0.18 μm CMOS工艺设计和实现了一种适用于100 Gbit/s以太网PCS链路的高速异步FIFO 芯片。采用双端口8T结构替代存储器,提高了工作速率。灵敏放大器利用锁存放大器和预充电技术来放大位线上微小信号,减少了传播延迟。为了减小读写时间,研究了存储单元晶体管尺寸对电平翻转时间的影响,既满足了快速访问的要求,又获得了高可靠性的信号传输。芯片(包括焊盘)面积为1.43 mm2。测量结果表明,该FIFO可工作于1.05 GHz,输出信号的眼图清晰,水平张开度达到0.91UI。当电源电压为1.8 V时,电路功耗为143.3 mW。该FIFO适用于16×6.25 Gbit/s以太网PCS链路系统。

Abstract

A high-speed asynchronous FIFO chip was designed in a 0.18 μm CMOS technology for 100 Gbit/s Ethernet PCS link system. Dual-port 8-transistor architecture instead of register in the memory cell was employed to increase transmission rate. Sense amplifier adopted latch-base amplifier combined with pre-charge technology to amplify the tiny signal between bitlines in reading phase for the smaller transmission latency. In order to reduce the writing time and the reading time, the effect of transistor size on the level flip time was also analyzed and simulated in detail, which not only met the requirement of rate, but also obtained the high reliability signal. The whole chip area including pads was 1.43 mm2. Test results show that the FIFO can operate over 1.05 GHz and the eye diagram of the output signal is clear with the horizontal opening degree reaching 0.91UI. The total power consumption is 143.3 mW at the supply voltage of 1.8 V. The designed FIFO is more suitable for 16×6.25 Gbit/s PCS link system.

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展永政, 李拓, 胡庆生, 邹晓峰, 王长红. 一种适用于100 Gbit/s以太网PCS的高速异步FIFO[J]. 微电子学, 2022, 52(5): 886. ZHAN Yongzheng, LI Tuo, HU Qingsheng, ZOU Xiaofeng, WANG Changhong. A High-Speed Asynchronous FIFO for 100 Gbit/s Ethernet PCS[J]. Microelectronics, 2022, 52(5): 886.

一种适用于100 Gbit/s以太网PCS的高速异步FIFO

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