高速流水线结构的大整数乘法器FPGA设计与实现

涂振兴; 王晓蕾; 杜高明; 李桢旻

doi:doi:10.13911/j.cnki.1004-3365.210095

微电子学, 2022, 52 (1): 6, 网络出版: 2022-06-14

高速流水线结构的大整数乘法器FPGA设计与实现

FPGA Design and Implementation of a Large Integer Multiplier with High Speed Pipeline Structure

论文大纲

涂振兴王晓蕾杜高明李桢旻

作者单位

合肥工业大学微电子设计研究所, 合肥 230601

高速流水线大整数乘法器 high speed pipeline large integer multiplier NTT NTT FPGA FPGA

摘要

大整数乘法是密态数据计算中最为耗时的基本运算操作, 提高大数乘法单元的计算速度在全同态加密机器学习等应用中尤为重要。提出了一种输入数据位宽为768 kbit的高速大整数乘法器设计方案, 将核心组件64 k点有限域快速数论变换(NTT)分解成16点NTT实现, 并通过算法分治处理, 细化16点NTT的流水线处理过程。采用加法和移位来实现模减计算单元, 并利用高效的无冲突地址生成算法完成数据交互, 实现大整数乘法的高速化。该乘法器最后被部署在Altera Stratix-V FPGA开发板上, 实验结果表明, 电路工作频率为169.23 MHz, 大整数乘法计算总体耗时0.317 ms。对比现有的硬件设计, 在速度性能上有1.2倍至7.3倍的提升。

Abstract

Large integer multiplication is the most time-consuming operation during encrypted data calculation. It is particularly important to improve large integer multiplier speed in machine learning based on fully homomorphic encryption. A design scheme of high speed 768 kbit large integer multiplier was proposed in this paper. The critical component 64k-point finite field number theory transform (NTT) was decomposed into 16-point NTT. And through dichotomy processing, the pipeline architecture of 16-point NTT was refined. To increase the speed of the multiplier, addition and shift were adopted to achieve the modular-subtraction unit, and data interaction was accomplished by using an efficient non-conflict address algorithm. The multiplier was deployed on the Altera Stratix-V FPGA development board. And the experimental results showed that the circuit had a working frequency of 169.23 MHz and took 0.317 ms to complete the large integer multiplication. Comparing with the state-of-the-art works, our speed performance was improved by 1.2 times to 7.3 times.

参考文献

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涂振兴, 王晓蕾, 杜高明, 李桢旻. 高速流水线结构的大整数乘法器FPGA设计与实现[J]. 微电子学, 2022, 52(1): 6. TU Zhenxing, WANG Xiaolei, DU Gaoming, LI Zhenmin. FPGA Design and Implementation of a Large Integer Multiplier with High Speed Pipeline Structure[J]. Microelectronics, 2022, 52(1): 6.

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