为了改善波束成形质量，基于相控阵芯片幅度和相位校准系统，提出了一种校准算法。在计算出每个状态的误差后，只需要遍历一次所有相控阵芯片的状态，就可以筛选出目标状态，生成查找表。筛选时，对每个状态的幅度误差、相位误差和使用CORDIC计算出的所有目标状态的RMS误差进行约束，可以使相控阵芯片实现误差(RMS)小于2°的6位移相(360°)和误差(RMS)小于0.3 dB的6位衰减(32 dB)。与穷举搜索和逐次逼近的方式相比，提出的校准算法节省了LUT的生成时间。根据此算法，使用65 nm CMOS工艺设计了一个自校准芯片，面积为584 613.16 μm2。

Based on the phased array chip amplitude and phase calibration system, a self-calibration algorithm is proposed to improve beamforming quality. After calculating the error of each state, only by traversing the errors of all phased array chip states once, the target state could be screened out and a Look-Up-Table (LUT) could be generated. During screening, the amplitude error and phase error of a single target state and the RMS error of all target states calculated by Coordinate Rotation Digital Computer (CORDIC) were constrained. Then, the phased array chip could achieve 6-bit phase shift (360°) with error (RMS) less than 2° and 6-bit attenuation (32 dB) with error (RMS) less than 0.3 dB. Compared with the exhaustive search and successive approximation methods, the calibration scheme saves LUT generation time. According to the algorithm, a self-calibration chip is designed in a 65 nm CMOS technology with die area of 584 613.16 μm2.