微电子学, 2022, 52 (1): 109, 网络出版: 2022-06-14  

界面电荷对圆柱形高k VDMOS的影响仿真研究

Simulation Study on the Effect of Interface Charge on Cylindrical High k VDMOS
作者单位
西南交通大学 电子工程系 集成电路设计实验室, 成都 610000
摘要
相比于传统VDMOS, 超结耐压层结构和高k介质耐压层结构VDMOS能实现更高的击穿电压和更低的导通电阻。通过仿真软件, 对3D圆柱形高k VDMOS具有、不具有界面电荷下的各种结构参数对电场分布、击穿电压和比导通电阻的影响进行了系统总结。研究和定性分析了击穿电压和比导通电阻随参数的变化趋势及其原因。对比导通电阻和击穿电压的折中关系进行了优化。该项研究对高k VDMOS的设计具有参考价值。
Abstract
Compared with traditional VDMOS, the superjunction and high k dielectric structure VDMOS could achieve higher breakdown voltage and lower on-resistance. The effects of various structural parameters on electric field distribution, breakdown voltage and specific on-resistance of 3D cylindrical high k VDMOS with and without interfacial charges were systematically summarized by simulation software. The variation trend and reason of breakdown voltage and specific on-resistance with parameters were studied and qualitatively analyzed. This study provided a reference for the design of high k VDMOS.
参考文献

[1] CHEN C P, HUANG M M. A vertical power MOSFET with an interdigitated drift region using high-k insulator [J]. IEEE Trans Elec Dev, 2012, 59(9): 2430-2437.

[2] 李维杰, 王兴, 王云峰, 等. NLDMOS器件性能优化及分析 [J]. 半导体光电, 2020, 41(1): 99-102, 140.

[3] SABUI G, SHEN Z J. Analytical calculation of breakdown voltage for dielectric RESURF power devices [J]. IEEE Elec Dev Lett, 2017, 38(99): 767-770.

[4] WANG Y, WANG Z, BAI T, et al. Modeling of breakdown voltage for SOI Trench LDMOS device based on conformal mapping [J]. IEEE Trans Elec Dev, 2018, 65(3): 1-7.

[5] CAMPBELL S A, GILMER D, WANG X C, et al. MOSFET transistors fabricated with high permitivity TiO2 dielectrics [J]. IEEE Trans Elec Dev, 1997, 44(1): 104-109.

[6] CHANG C W, DENG C K, HUANG J J, et al. High-performance poly-Si TFTs with Pr2O3 gate dielectric [J]. IEEE Elec Dev Lett, 2008, 29(1): 96-98.

[7] NADIMI E, ROLL G, KUPKE S, et al. The degradation process of high-k SiO2/HfO2 gate-stacks: a combined experimental and first principles investigation [J]. IEEE Trans Elec Dev, 2014, 61(5): 1278-1283.

[8] PARK J H, JANG G S, LEE S K, et al. High-performance poly-Si thin-film transistor with high-k ZrTiO4 gate dielectric [J]. IEEE Elec Dev Lett, 2015, 36(9): 920-622.

[9] ZHU Z N, JIE X, ZHAO Z Y, et al. Conduction mechanism in SrTiO3-based field-effect transistors [J]. IEEE Trans Elec Dev, 2015, 62(7): 2352-2355.

[10] CHEN X P. Super-junction voltage sustaining layer with alternating semiconductor and high-K dielectric regions [M]. Shanghai: Tongji University Press, 2007: 227-228.

[11] SAKAKIBARA J, NODA Y, SHIBATA T, et al. 600 V-class super junction MOSFET with high aspect ratio P/N columns structure [C] // IEEE Proceed Int Symp Power Semicond Dev & IC. Florida, FL, USA. 2008: 299-302.

[12] 钱照明, 盛况. 大功率半导体器件的发展与展望 [J]. 大功率变流技术, 2010(1): 1-9.

[13] WANG Q, WANG P, JIANG Y H, et al. A new SJ VDMOS with an extended HK dielectric-filling trench [C] // IEEE Proceed ICSICT. Xi’an, China. 2012: 1-3.

[14] LYU X J, CHEN X P. Vertical power Hk-MOSFET of hexagonal layout [J]. IEEE Trans Elec Dev, 2013, 60(5): 1709-1715.

[15] ZHOU J, HUANG C F, CHENG C H, et al. A comprehensive analytical study of dielectric modulated drift regions - part I: static characteristics [J]. IEEE Trans Elec Dev, 2016, 63(6): 1-6.

[16] WANG Z G,WANG X, KUO J B. Modeling power vertical high-k MOS device with interface charges via superposition methodology-breakdown voltage and specific on-resistance [J]. IEEE Trans Elec Dev, 2018, 65(11): 4947-4954.

刘乙. 界面电荷对圆柱形高k VDMOS的影响仿真研究[J]. 微电子学, 2022, 52(1): 109. LIU Yi. Simulation Study on the Effect of Interface Charge on Cylindrical High k VDMOS[J]. Microelectronics, 2022, 52(1): 109.

关于本站 Cookie 的使用提示

中国光学期刊网使用基于 cookie 的技术来更好地为您提供各项服务,点击此处了解我们的隐私策略。 如您需继续使用本网站,请您授权我们使用本地 cookie 来保存部分信息。
全站搜索
您最值得信赖的光电行业旗舰网络服务平台!