基于0.18 μm CMOS工艺设计与实现了一种14位85 MS/s流水线型模数转换器(ADC)。采用多种低功耗设计技术来降低系统功耗和面积,包括无采样保持电路前端和运算放大器共享等技术。在无数字校准的条件下,在3.3 V电源电压、85 MHz的时钟频率和70 MHz正弦输入信号频率下,达到了67.9 dBFS的信噪比(SNR)以及82.2 dBFS的无杂散动态范围(SFDR)。该ADC功耗为322 mW,面积为0.6 mm2,适合用于需求低功耗ADC的通信系统中。

A 14-bit 85 MS/s pipelined analog-to-digital converter (ADC) was designed and implemented in a 0.18 μm CMOS process. Several techniques such as SHA-less front-end and amplifier sharing had been adopted to reduce the ADC’s power consumption and area. Under 3.3 V power supply, 85 MHz clock and 70 MHz sine input, the ADC achieved an SNR of 67.9 dBFS and an SFDR of 82.2 dBFS without calibration. It consumed 322 mW with an area of 0.6 mm2, which was suitable for communication systems where lower power ADCs were needed.