采用0.18 μm CMOS工艺设计了一种四通道16位250 MS/s A/D转换器(ADC)。该转换器采用时间交织与流水线结合的结构,内部包含基准、时钟和数字校准等单元。芯片测试结果表明,开启数字校准后,动态指标SNR、SFDR分别达到73 dBFS和90 dBFS,通道功耗为0.25 W,优值(FoM)为0.25 pJ/(conv·step)。

A 4-channel 16 bit 250 MS/s A/D converter was designed in a 0.18 μm CMOS process. In the converter, a time interleaved structure combined with pipelined structure was adopted, which consisted of reference, clock and digital correction units. The chip tested results showed that the dynamic specification achieved a SNR of 73 dBFS and a SFDR of 90 dBFS with digital calibration. The ADC channel power was 0.25 W, and the corresponding figure-of-merit (FoM) was 22 fJ/(conv·step).