一种环路带宽自适应调整的时钟数据恢复电路

针对SONTE OC-192、PCIE3.0、USB3.2等协议在串行时钟数据恢复时对抖动容限、环路稳定时间的要求,提出了一种环路带宽自适应调整、半速率相位插值的时钟数据恢复电路(CDR)。设计了自适应控制电路,能适时动态调整环路带宽,实现串行信号时钟恢复过程中环路的快速稳定,提高了时钟数据恢复电路抖动容限。增加了补偿型相位插值控制器,进一步降低了数据接收误码率。该CDR电路基于55 nm CMOS工艺设计,数据输入范围为8~11.5 Gbit/s。采用随机码PRBS31对CDR电路的仿真测试结果表明,稳定时间小于400 ns,输入抖动容限大于0.55UI@10 MHz,功耗小于23 mW。

Abstract

Aiming at the requirements of SONTE OC-192, PCIE3.0, USB3.2 and other protocols for jitter tolerance and loop stability time during serial clock data recovery, a half rate phase interpolation CDR circuit with adaptive loop bandwidth adjustment was proposed. The adaptive control circuit was designed to dynamically adjust the loop bandwidth in a timely manner to achieve fast loop stability during serial signal clock recovery and improve the jitter tolerance of the clock data recovery circuit. A compensated phase interpolation controller was added to further reduce the data reception BER. The CDR circuit was designed in a 55 nm CMOS process with a data input range of 8~11.5 Gbit/s. The random code PRBS31 was used. The simulation test results showed that the stabilization time was less than 400 ns, the input jitter tolerance was more than 0.55UI@10 MHz, and the power consumption was less than 23 mW.

参考文献

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常承, 韦保林, 韦雪明, 侯伶俐, 徐卫林. 一种环路带宽自适应调整的时钟数据恢复电路[J]. 微电子学, 2022, 52(4): 656. CHANG Cheng, WEI Baolin, WEI Xueming, HOU Lingli, XU Weilin. A Clock Data Recovery Circuit with Adaptive Loop Bandwidth Adjustment[J]. Microelectronics, 2022, 52(4): 656.

一种环路带宽自适应调整的时钟数据恢复电路

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