在高压宽输入范围的芯片中,高压电源一般不直接作为带隙基准电路的电源。传统方案采用齐纳二极管加源随器将高压输入转换为低压电源，为带隙基准供电,然而低压电源波动过大,降低了带隙基准的PSRR。电源由反馈环路产生,可以提供高PSRR性能。文章提出了一种输入电压范围为5~65 V,通过闭环负反馈产生低压电源和1.2 V基准电压的带隙基准电路,适用于宽输入电压芯片，如Buck、电机驱动或模拟ASIC芯片。该带隙基准电路的电源是将自身产生的电流流经PMOS,由PMOS的VGS确定。因此低压电源不随输入电压变化,线性调整率极低。该电路由预处理电路、启动电路和带隙基准电路组成,采用负反馈稳压设计,不使用齐纳二极管,不引入额外的掩膜层,降低了电路成本。在CSMC 0.25 μm BCD工艺下,基准电压线性调整率低至0.000 091%,输入电压在5~65 V范围内基准变化小于1 μV,低频PSRR为-160 dB@100 Hz,温度系数为2.8×10-5/℃。

In high voltage wide input range chips, the high voltage power generally is not directly used as the power supply of the bandgap reference circuit. A Zener diode and source follower are always used to generate a low-voltage power supply for the bandgap in traditional scheme. However, the low-voltage power supply is fluctuated easily, which reduces the PSRR (power supply rejection ratio) of the bandgap. When the power supply of the bandgap is generated by the feedback loop, the reference may obtain a high PSRR performance. In this paper, a bandgap circuit with a wide input range of 5~65 V was proposed for the applications of bucks, motor drivers or analog ASIC chips. The closed-loop negative feedback circuit generated a low voltage power supply and a 1.2 V reference voltage. The power of the bandgap circuit was determined by the VGS of the PMOS, and the current of the PMOS was generated by the bandgap circuit. Therefore, the low voltage power supply made no reference to input voltage, which improved the PSRR of the reference voltage. The circuit was composed of a preprocessing circuit, a start-up circuit and a bandgap circuit. No additional mask layer and Zener diode were used in this design, which reduced the circuit cost. Under CSMC 0.25 μm BCD process, this design achieved a bandgap reference voltage which linear adjustment rate was 0.000 091%, PSRR under low frequency was -160 dB@100 Hz and the temperature coefficient was 2.8×10-5/℃. The reference voltage variation was less than 1 μV when input voltage varied in the range of 5~65 V.