针对MDAC中采样电容失配会降低ADC输出非线性性能的问题,提出了一种流水线ADC的前台数字校准技术。该前台数字校准技术利用ADC输出积分非线性的相对偏差提取误差,利用简单的多路选择运算单元进行误差补偿。在此基础上,采用Verilog HDL实现了RTL级描述并成功流片。仿真和测试结果表明,该校准算法能够提升ADC输出性能。

A foreground digital calibration technology for pipelined ADC was introduced. The calibration was mainly aimed at the sampling capacitor mismatch in MDAC, which increased the nonlinearity of ADC output. The proposed foreground digital calibration technology used the relative deviation of the integral nonlinearity of the ADC output to extract the error, and used a simple multi-channel selection operation unit to compensate the error. On this basis, Verilog HDL was used to realize RTL level description, and the circuit was taped out successfully. Simulation and test results showed that the proposed calibration algorithm could improve the output performance of ADC.