Neuromorphic photonic computing has emerged as a competitive computing paradigm to overcome the bottlenecks of the von-Neumann architecture. Linear weighting and nonlinear spike activation are two fundamental functions of a photonic spiking neural network (PSNN). However, they are separately implemented with different photonic materials and devices, hindering the large-scale integration of PSNN. Here, we propose, fabricate and experimentally demonstrate a photonic neuro-synaptic chip enabling the simultaneous implementation of linear weighting and nonlinear spike activation based on a distributed feedback (DFB) laser with a saturable absorber (DFB-SA). A prototypical system is experimentally constructed to demonstrate the parallel weighted function and nonlinear spike activation. Furthermore, a four-channel DFB-SA laser array is fabricated for realizing matrix convolution of a spiking convolutional neural network, achieving a recognition accuracy of 87% for the MNIST dataset. The fabricated neuro-synaptic chip offers a fundamental building block to construct the large-scale integrated PSNN chip.

Spiking neural networks (SNNs) utilize brain-like spatiotemporal spike encoding for simulating brain functions. Photonic SNN offers an ultrahigh speed and power efficiency platform for implementing high-performance neuromorphic computing. Here, we proposed a multi-synaptic photonic SNN, combining the modified remote supervised learning with delay-weight co-training to achieve pattern classification. The impact of multi-synaptic connections and the robustness of the network were investigated through numerical simulations. In addition, the collaborative computing of algorithm and hardware was demonstrated based on a fabricated integrated distributed feedback laser with a saturable absorber (DFB-SA), where 10 different noisy digital patterns were successfully classified. A functional photonic SNN that far exceeds the scale limit of hardware integration was achieved based on time-division multiplexing, demonstrating the capability of hardware-algorithm co-computation.