随着芯片的集成度越来越高, 物理设计布局阶段的拥塞问题越发严重。提出了一种基于溢出值的局部拥塞消除技术, 根据溢出值选择出拥塞密度最高的拥塞区域, 然后基于模拟退火算法对该区域内的高引脚单元设置合适大小的隔离区域, 以缓解局部拥塞。将提出的方法应用于SMIC 180 nm工艺的四万门设计和SMIC 55 nm工艺的七千门设计进行优化。相较于Synopsys的ICC工具的拥塞优化结果, 提出的方法使设计规则违例下降48%, 短路违例下降52%, 总线长缩短5%, 比现有文献的布线质量更好。

With a significant increase in chip’s integration, congestion in the placement stage of physical design had become growingly severe. Therefore, an overflow-based local congestion elimination technique was designed. Firstly, the congestion region with the highest congestion density was selected according to the overflow value. Then keepout margins of appropriate size were set for the high-pin cells in that region on the basis of simulated annealing algorithm to alleviate local congestion. The method was applied to a 40 000-gate design of the SMIC 180 nm process, and a 7 000-gate design of the SMIC 55 nm process. Compared with the optimization results of Synopsys’s ICC software, the proposed method could reduce design rule violations by 48%, shorts by 52% and total wire length by 5%. It also achieved better routing quality than existing literatures.