一种低延迟折叠插值12位1.5 GS/s ADC

基于4级级联折叠插值架构,提出了一种12位ADC。电路采用0.18 μm SiGe BiCMOS工艺设计。单核达到1.5 GS/s的转换速度,接口输出为2-lane LVDS,延迟时间小于7 ns。前端采样保持电路和折叠插值量化器采用纯双极设计,在不修调的情况下可达到12位量化精度。最后，给出版图设计要点和测试结果。

Abstract

Based on a 4-stage cascade folding interpolation architecture, a 12-bit ADC was presented. The circuit was designed in a 0.18 μm SiGe BiCMOS process. The single core achieved a conversion speed of 1.5 GS/s, the output interface was 2-lane LVDS, and the latency was less than 7 ns. The front-end sample/hold circuit and folding interpolation quantizer adopted pure bipolar design, which could achieve 12 bit quantization accuracy without trimming. Finally, the design points and test results of the published layout were given.

参考文献

[1] ALI A M A, DINC H, BHORASKAR P, et al. A 14 b 2.5 GS/s and 5 GS/s RF sampling ADC with background calibration and dither ［C］// VLSI-Circuits. Honolulu, HI, USA. 2016: 206-207.

[2] ALI A M A, DINC H , BHORASKAR P , et al. A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration ［J］. IEEE J Sol Sta Circ, 2014, 49(12): 2857-2867.

[3] SETTERBERG B, POULTON K, RAY S, et al. A 14 b 2.5 GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction ［C］// ISSCC Dig Pap. San Francisco, CA, USA. 2013: 466-468.

[4] RAZZAGHI A, TAM S W, KALKHORAN P, et al. A single-channel 10 b 1 GS/s ADC with 1-cycle latency using pipelined cascaded folding ［C］// IEEE Bipolar/BiCMOS Circ Tech Meet. Monterey, CA, USA. 2008: 265-268.

[5] CHANTIER N, NICOLAS S, MORISSON R, et al. 12 bit 1.5 GS/s L-band ADC on 200 GHz SiGeC technology ［C］// IEEE CIE Int Conf Radar. Chengdu, China. 2012: 265-268.

[6] 贺文伟. 超高速折叠插值ADC关键技术的研究与设计［D］. 南京: 东南大学, 2017.

[7] 李国栋. 高速折叠插值模数转换器的设计［D］. 南京:东南大学, 2019.

[8] 张宝娣. 10位高速ADC的研究与设计［D］. 合肥: 合肥工业大学, 2019.

[9] DINC H, ALLEN P E. A 1.2 GSample/s double-switching CMOS THA with -62 dB THD ［J］. IEEE J Sol Sta Circ, 2009, 44(3): 848-861.

[10] BOCK J, SCHAFER H, AUFINGER K, et al. SiGe bipolar technology for automotive radar applications ［C］// Bipolar/BiCMOS Circ Tech Meet. Montreal, Canada. 2004: 84-87.

[11] 孙伟, 王永禄, 杨鑫, 等.一种12位2 GS/s BiCMOS采样保持电路［J］. 微电子学, 2019, 49(3): 326-330.

[12] ZIMMER T, BCK J, BUCHALI F, et al. SiGe HBTs and BiCMOS technology for present and future millimeter-wave systems ［J］. IEEE J Microwave, 2021, 1(1): 288-298.

徐鸣远, 付东兵, 朱璨, 张磊, 王妍, 李梁. 一种低延迟折叠插值12位1.5 GS/s ADC[J]. 微电子学, 2022, 52(4): 597. XU Mingyuan, FU Dongbing, ZHU Can, ZHANG Lei, WANG Yan, LI Liang. A Low Latency Folding and Interpolation 12 bit 1.5 GS/s ADC[J]. Microelectronics, 2022, 52(4): 597.

一种低延迟折叠插值12位1.5 GS/s ADC

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